The present invention relates, in general, to field effect transistors, and more particularly to short channel length field effect transistors having low threshold voltages and enhanced punchthrough resistance.
Field effect transistor (FET) devices are becoming increasingly important in low voltage power applications including personal communication (e.g., pagers, cellular phones, etc.) and portable computers. With lower power consumption being a primary requirement with these applications, FET devices are being designed to operate at supply voltages less than 3.5 volts. However, semiconductor device parameters such as threshold voltage, subthreshold leakage currents, parasitic source/drain capacitances, and source to drain punchthrough typically limit the performance of low power semiconductor devices.
Source to drain punchthrough generally takes place with the merging of the source and drain depletion regions. When this occurs, the gate region is unable to control carriers in the channel region. The device basically becomes a short circuit and is considered uncontrollable. One previously known method to overcome this problem is to increase the uniform channel doping with a channel implant to inhibit punchthrough. This approach, however, is not desirable for low voltage and low power applications due to the loss in device performance. For effective low power applications the threshold voltage of the devices should be below 0.6 volts.
An alternative approach is to maintain a lower channel doping concentration and place highly doped regions in a bilateral fashion on both the source and drain sides. These regions are often termed halo or punchthrough stops. This approach inhibits punchthrough while maintaining lower threshold voltages (e.g., on the order of 0.3 volts). However, this approach suffers from higher capacitance and reduced drive capability (i.e., reduced transconductance), which in turn results in slower switching speeds.
As each device parameter is optimized for low power applications, there are two viewpoints that need to be considered when evaluating a low power device structure. The first perspective involves the physics of the device which determines the device performance and evaluates the interaction between all device parameters. For instance, there are several methods provided in the prior art that can be used to set the threshold voltage of semiconductor device. Each has its merits as a method to set threshold voltage, but the technique should also be judged based on the impact on all device parameters such as subthreshold leakage, punchthrough voltage, etc.
The second perspective that must be considered when evaluating a low power device structure determines the manufacturability of the proposed device. Again, any of the previously know methods to set threshold voltage are adequate to manufacture a limited number of devices in a research environment. These previously known methods, however, may not be effective when millions of devices must be manufactured in a high volume cost sensitive production facility. The method used to fabricate the low power/low voltage device must be tolerant of normal process variance in device parameters such as channel length, channel depth, or gate oxide thickness. The proposed method should be robust enough to withstand normal variations in these parameters and produce devices that operate over the required performance conditions.
Accordingly, it would be advantageous to have an FET device that possesses a low and controlled threshold voltage, that is punchthrough resistant, and that exhibits good switching characteristics. It would be of further advantage to provide such an FET device using conventional techniques to simplify its integration into existing structures.